Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
As integration increases and device feature size decreases, the thickness of gate dielectric layers decreases. As device feature sizes shrink to 0.25 microns and under, the gate dielectric layer thickness is reduced to below about 80 .ANG., thereby generating various problems, such as impurity penetration through the gate dielectric layer into the semiconductor substrate with consequential shorting out of the transistor and/or otherwise decreasing device reliability. For example, when forming P-channel MOS transistors, boron is typically implanted into the gate electrode layer before etching to form the gate electrode. Such implanted boron easily diffuses through a thin gate dielectric layer into the underlying silicon substrate and shorts out or shifts the transistor.
A conventional approach in addressing such an impurity penetration problem comprises implanting nitrogen into the gate electrode layer before forming the gate electrode by conventional photolithographic and etching techniques. For example, adverting to FIG. 1, a gate dielectric layer 11, such as a silicon dioxide layer, is formed at a thickness less than about 80 .ANG. on semiconductor substrate 10, typically silicon doped with an appropriate impurity, such as an N-type impurity. A conductive layer 12, such as polycrystalline silicon, is formed on gate dielectric layer 11 and serves as the gate electrode layer. In order to suppress subsequent dopant penetration through gate dielectric layer 11, such as boron penetration, nitrogen ions are implanted into gate electrode layer 12, as indicated by arrows 14, at a dosage of about 1.times.10.sup.13 atoms cm.sup.-2 to about 1.times.10.sup.16 atoms cm.sup.-2. Such high nitrogen implantation dosages cause crystallographic damage to gate electrode layer 12 and consequential amorphization of an upper portion thereof indicated by "x" marks 15. Such a nitrogen induced amorphous region can extend through about fifty percent of the thickness of polycrystalline silicon layer 12.
It was found that the nitrogen induced amorphous portion exhibits etching characteristics different from the remaining crystalline portion of gate electrode layer 12. Upon masking and etching to form gate electrode 22 on semiconductor substrate 10 with gate dielectric layer 21 therebetween, as shown in FIG. 2, the side surfaces of gate electrode 22 are neither substantially parallel to one another nor substantially perpendicular to the upper surface of semiconductor substrate 10, as desired for optimum performance and reliability. Instead, as shown in FIG. 2, the side surfaces 23 of etched gate electrode 22 are concave forming an hourglass type profile. Such an etch profile could cause transistor performance degradation, e.g., transistor drive current non-uniformities and asymmetry.
Thus, the conventional solution to the problem of impurity penetration through thin gate dielectric layers comprising remedial nitrogen ion implantation is problematic with respect to the etch profile of the subsequently patterned gate electrode. Accordingly, there exists a need for a method of manufacturing a semiconductor device wherein impurity penetration through a thin gate dielectric layer is prevented by nitrogen ion implantation without adverse impact on the etch profile of the subsequently formed gate electrode.